1 offset adjust v1 2 offset adjust i1 3 analog input 1 4 analog input 2 5 analog ground 6 s/h1 out 7 s/h1 rout 8 s/h2 summing node 9 offset adjust v2 10 offset adjust i2 11 s/h1 command 12 s/h2 command input/output connections 24 +15v analog supply 23 analog ground 22 v out 21 analog ground 20 a/d clock2 19 a/d clock2 18 a/d clock1 17 a/d clock1 16 +5v digital supply 15 digital ground 14 analog ground 13 C15v analog supply features use with 10 to 14-bit a/d converters 1.25 megapixels/second minimum throughput (14 bits) 10v input/output ranges, gain = C1 low noise, 200vrms two independent s/h amplifiers gain matching between s/h's offset adjustments for each s/h four external a/d control lines small package, 24-pin ceramic ddip low power, 700mw low cost general description the CDS-1401 is an application-specific, correlated double sampling (cds) circuit designed for electronic-imaging applications that employ ccds (charge coupled devices) as their photodetector. the CDS-1401 has been optimized for use in digital video applications that employ 10 to 14-bit a/d converters. the low-noise CDS-1401 can accurately determine each pixels true video signal level by sequentially sampling the pixels offset signal and its video signal and subtracting the two. the result is that the consequences of residual charge, charge injection and low-frequency ktc noise on the ccds output floating capacitor are effectively eliminated. the CDS-1401 can also be used as a dual sample-hold amplifier in a data acquisition system. the CDS-1401 contains two sample-hold amplifiers and appropriate support/control circuitry. features include independent offset-adjust capability for each s/h, adjustment for matching gain between the two s/hs, and four control pin function pin function innovation and ex c ell e n c e ? ? figure 1. CDS-1401 functional block diagram lines for triggering the a/d converter used in conjunction with the CDS-1401. the cds circuits ping-pong timing approach (the offset signal of the n+1 pixel can be acquired while the video output of the nth pixel is being converted) guarantees a minimum throughput, in a 14-bit application, of 1.25mhz. in other words, the true video signal (minus offset) will be available (continued on page 4-5) CDS-1401 14-bit, fast-settling correlated double sampling circuit s/h 2 offset adjust v1 1 offset adjust i1 2 analog input 1 3 s/h 1 offset adjust v2 9 offset adjust i2 10 analog input 2 4 s/h1 command 11 s/h2 command 12 5, 14, 21, 23 analog ground 24 +15v supply 16 +5v digital supply 15 digital ground 7 s/h1 rout 8 s/h2 summing node 22 v out 18 a/d clock 1 6 s/h1 out optional 17 a/d clock 1 19 a/d clock 2 20 a/d clock 2 c h = 100pf 1k w 100 w 100k w 1k w c h = 100pf 100k w 1k w 900 w 1k w 13 C15v supply C + C + datel, inc., 11 cabot boulevard, mansfield, ma 02048-1151 (u.s.a.) tel: (508) 339-3000 fax: (508) 339-6356 for immediate assistance (800) 233-2765
2 CDS-1401 ? ? parameters min. typ. max. units operating temp. range, case CDS-1401mc 0 +70 c CDS-1401mm C55 +125 c thermal impedance q jc 5 c/w q ca 22 c/w storage temperature range C65 +150 c package type 24-pin, metal-sealed, ceramic ddip weight 0.42 ounces(12 grams) +25c 0 to +70c C55 to +125c analog inputs min. typ. max. min. typ. max. min. typ. max. units input voltage range 10 10 10 volts input resistance 1000 1000 1000 ohms input capacitance 715715715pf digital inputs logic levels logic "1" +2 +2 +2 volts logic "0" +0.8 +0.8 +0.8 volts logic loading "1" +10 +10 +10 a logic loading "0" C10 C10 C10 a performance sample mode offset error - s/h1 1 10 2 10 4 10 mv gain error - s/h1 0.2 1 0.25 1 0.3 1.5 % pedestal - s/h1 15 35 15 35 15 35 mv sample mode offset error - s/h2 1 10 2 10 4 10 mv gain error - s/h2 0.2 1 0.25 1 0.3 1.5 % pedestal - s/h2 15 35 15 35 15 35 mv sample mode offset error - cds 1 10 2 10 4 10 mv differential gain error - cds 0.25 1 0.3 1 0.35 1.5 % pedestal - cds 15 35 15 35 15 35 mv pixel rate (14-bit settling) 1.25 1.25 1.25 mhz input bandwidth, 5v small signal (C20db input) 7 7 7 mhz large signal (C0.5db input) 5 5 5 mhz slew rate 80 80 80 v/s aperture delay time 101010ns aperture uncertainty 555ps rms s/h acquisition time (to 0.003%, 10v step) 340 400 350 400 350 400 ns hold mode settling time (to 0.15mv) tbd tbd tbd ns noise 200 200 200 vr ms feedthrough rejection 727272db overvoltage recovery time 400 400 400 ns s/h saturation voltage 12.5 12.5 12.5 volts droop rate 0.004 0.02 0.4 2 0.8 4 mv/s analog outputs a output voltage range 10 10 10 volts output impedance 0.5 0.5 0.5 ohms output current 20 20 20 ma digital outputs logic levels logic "1" +3.9 +3.9 +3.9 volts logic "0" +0.4 +0.4 +0.4 volts logic loading "1" C4 C4 C4 ma logic loading "0" +4 +4 +4 ma absolute maximum ratings parameters limits units +15v supply (pin 24) 0 to +16 volts C15v supply (pin 13) 0 to C16 volts +5v supply (pin 16) 0 to +6 volts digital inputs (pins 11, 12) C0.3 to +v dd +0.3 volts analog inputs (pins 3, 4) 12 volts lead temp. (10 seconds) 300 c pins 3 and 4. see figure 4 for relationship between input voltage, accuracy, and acquisition time. a pins 6 and 22. functional specifications (t a = +25c, vcc = 15v, +v dd = +5v, pixel rate = 1.25mhz, and a minimum warmup time of two minutes unless otherwise noted.) physical/environmental
3 ? ? CDS-1401 +25c 0 to +70c C55 to +125c power requirements min. typ. max. min. typ. max. min. typ. max. units power supply ranges +15v supply +14.75 +15.0 +15.25 +14.75 +15.0 +15.25 +14.75 +15.0 +15.25 volts C15v supply C14.75 C15.0 C15.25 C14.75 C15.0 C15.25 C14.75 C15.0 C15.25 volts +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 volts power supply currents +15v supply +23 +27 +23 +27 +23 +27 ma C15v supply C23 C27 C23 C27 C23 C27 ma +5v supply +1 +2 +1 +2 +1 +2 ma power dissipation 700 850 700 850 700 850 mw power supply rejection 100 100 100 db focal plane arrays, charge coupled devices, etc.) have unique output characteristics that call for specific analog-signal- processing (asp) functions at their outputs. charge coupled devices (ccds), in particular, display a number of unique characteristics. among them is the fact that the offset error associated with each individual pixel (i.e., the apparent photonic content of that pixel after having had no light incident upon it) changes each and every time that particular pixel is accessed. most of us think of an offset as a constant parameter that either can be compensated for (by performing an offset adjustment) or can be measured, recorded, and subtracted from subsequent readings to yield more accurate data. contending with an offset that varies from reading to reading requires measuring and recording (or capturing and storing) the offset each and every time, so it can be subtracted from each subsequent data reading. the double sampling aspect of cds refers to the operation of sampling and storing/recording a given pixels offset and then sampling the same pixels output an instant later (with both the offset and the video signal present) and subsequently subtracting the two values to yield what is referred to as the valid video output for that pixel. the correlated in cds refers to the fact that the two samples must be taken close together in time because the offset is constantly varying. reasons for this phenomena are discussed below. at the output of all ccds, transported pixel charge (electrons) is converted to a voltage by depositing the charge onto a capacitor (usually called the output or floating capacitor). the voltage that develops across this capacitor is obviously proportional to the amount of deposited charge (i.e., the number of electrons) according to d v = d q/c. once settled, the resulting capacitor voltage is buffered and brought to the ccds output pin as a signal whose amplitude is proportional to the total number of photons incident upon the relevant pixel. after the output signal has been recorded, the floating capacitor is discharged (reset, clamped, dumped) and made ready to accept charge from the next pixel. this is when the problems begin. (this is a somewhat oversimplified functional description correlated double sampling all photodetector elements (photodiodes, photomultiplier tubes, general description (continued) at the output of the CDS-1401 every 800ns. this correlates with the fact that an acquisition time of 400ns is required for each internal s/h amplifier (10v step setting to 0.003%). the input and output of the CDS-1401 can swing up to 10 volts. the functionally complete CDS-1401 is packaged in a single, 24-pin, ceramic ddip. it operates from 15v and +5v supplies and consumes 700mw. though the CDS-1401s approach to cds appears straightforward (see description of operation), the circuit actually exploits an elegant architecture whose tradeoffs enable it to offer wide-bandwidth, low-noise and high- throughput combinations unachievable until now. the cds- 1401 is a generic type of circuit that can be used with almost any 10 to 14-bit a/d converter. however, datel does offer a/d converters that are optimized for use with the CDS-1401. technical notes 1. to achieve specified performance, all power supply pins should be bypassed with 2.2f tantalum capacitors in parallel with 0.1f ceramic capacitors. all analog ground (pins 5, 14, 21 and 23) and digital ground (pin 15) pins should be tied to a large analog ground plane beneath the package. 2. in the cds configuration, to avoid saturation of the s/h amplifiers, the maximum analog inputs and conditions are as follows: analog input 1 < 12v (analog input 1 C analog input 2) < 12v 3. the combined video and reference/offset signal from the ccd array must be applied to s/h2, while the reference/ offset signal is applied to s/h1. 4. to use as a cds circuit, tie pin 8 (s/h2 summing node) to either pin 6 (s/h1 out), through a 200 ohm potentiometer, or directly to pin 7 (s/h1 rout). in both cases, the ccd's output is tied to pins 3 (analog input 1) and 4 (analog input 2). as shown in figure 5, the 200 w potentiometer is for gain matching. 5. to use as a dual s/h, leave pin 7 (s/h1 rout) and pin 8 (s/h2 summing node) floating. pin 6 (s/h1 out) will be the output of s/h1 and pin 22 (v out) will be the output of s/h2. 6. see figure 4 for acquisition time versus accuracy and input voltage step amplitude.
4 CDS-1401 ? ? figure 2. CDS-1401 typical timing diagram explanation in that the floating capacitor is not usually discharged but, in fact, recharged to some predetermined dc voltage, usually called the reference level. the pixel offset appears as an output deviation from that reference level.) the floating capacitor is normally discharged (charged) via a shunt switch (typically a fet structure) that has a non-zero on resistance. when the switch is on, its effective series resistance exhibits thermal noise (johnson noise) due to the random motion of thermally energized charge. because the shunt switch is in parallel with the floating capacitor, the instantaneous value of the thermal noise (expressed in either volts or electrons) appears across the cap. when the shunt switch is opened, charge/voltage is left on the floating cap. the magnitude of this captured noise voltage is a function of absolute temperature (t), the value of the floating capacitor (c) and boltzmans constant (k). it is commonly referred to as ktc noise. the second contributor to the constantly varying pixel offsets is the fact that, at high pixel rates, the floating capacitor never has time to fully discharge (charge) during the period in which its shunt switch is closed. there is always some residual charge left on the cap, and the amount of this charge varies as a function of what was the total charge held during the previous pixel. this amount of residual charge is, in fact, deterministic (if you know the previous charge and the number of time constants in the discharge period), however, it is less of a contributor than ktc noise. the third major contributor to pixel offset is the fact that as the shunt fet is turned off, the voltage across (and the charge stored on) its parasitic junction capacitances changes. the result is an injection of excess charge onto the floating cap causing a voltage step normally called a pedestal. the fourth major contributor to pixel offset is a low-frequency noise component (usually called 1/f noise or pink noise) associated with the ccds output buffer amplifier. due to all of these contributing factors, "pixel offsets" vary from sample to sample in an inconsistent, unpredictable manner. traditional approach to cds there are a number of techniques for dealing with the varying- offset idiosyncrasy of ccds. the most prevalent has been what can be called the sample-sample-subtract technique. this approach requires the use of two high-speed sample-hold (s/h) amplifiers and a difference amplifier. the first s/h is used to acquire and hold a given pixels offset. immediately after that, the second s/h acquires and holds the same pixels offset+video signal. after both the s/h outputs have fully settled, the difference amplifier subtracts the offset from the offset+video yielding the valid video signal. CDS-1401 approach (see figure 1) the datel CDS-1401 takes a slightly different, though clearly superior, approach to cds. it can be called the sample- subtract-sample approach. note that the CDS-1401 has been configured to offer the greatest amount of user flexibility. its two s/h circuits function independently. they have separate input and output pins. each has its own independent control lines. the control-line signals are delayed, buffered, and brought back out of the analog input for cds (pins 3 and 4 are tied) s/h 1 (pin 11) a/d clock 1 (pin 17) s/h 2 (pin 12) a/d clock 1 (pin 18) a/d clock 2 (pin 19) a/d clock 2 (pin 20) voltage output video signal n-1 video signal n (ccd output) 100ns typ. 30ns typ. 30ns typ. note: not drawn to scale reset n offset n offset + video n reset n+1 offset n+1 offset + video n+1 100ns typ. hold hold
5 ? ? CDS-1401 track mode when large, high-speed transients (normally associated with clock edges) are occurring throughout the system. this could result in the s/h amplifiers being driven into saturation, and they may not recover in time to accurately acquire their next signal. for example, s/h1 should not be commanded into the sample mode until all transients associated with the opening of the shunt switch have begun to decay. similarly, s/h2 should not be driven into the sample mode until all transients associated with the clocking of pixel charge onto the output capacitor have begun to decay. therefore, it is generally not a good practice to use the same clock edge to drive s/h1 into hold (holding the offset) and s/h2 into sample (to acquire the offset + video signal). s/h's that are in their signal-acquisition modes should be left there as long as possible (so all signals can settle) and be driven into their hold modes before any system transients occur. in figure 2, s/h1 is driven into the sample mode shortly after the transient from the shunt switch has begun to decay. s/h1 is then kept in the sample mode while the offset signal and the s/h output settle. s/h1 is driven into hold just prior to the system clock pulse(s) that transfers the next pixel charge onto the output capacitor. as soon as the transients/noise associated with the charge transport begins to decay, s/h2 can be driven into the sample mode. s/h2 can then be left in the sample mode until just before the reset pulse for the output capacitor. in figure 2, s/h's 1 and 2 both have the same acquisition time. if the pixel-to-pixel amplitude variation of offset signals is much package so they can be used to control other circuit functions. each s/h has two pins for offset adjusting (if required), one for current and one for voltage. in normal operation, the output signal of the ccd is applied simultaneously to the inputs (pins 3 and 4) of both s/h amplifiers. s/h1 will normally be used to capture and hold each pixels offset signal. therefore, s/h1 is initially in its signal-acquisition mode (logic 1 applied to pin 11, s/h1 command). this is also called the sample or track mode. following a brief interval during which the output of the ccd and the output of s/h1 are allowed to settle, s/h1 is driven into its hold mode by applying a logic 0 to pin 11. s/h1 is now holding the pixels offset value. in most straightforward configurations, the output of s/h1 is connected to the summing node of s/h2 by connecting pin 7 (s/h1 rout) to pin 8 (s/h2 summing node). when the offset+video signal appears at the output of the ccd, s/h2 is driven into its signal acquisition mode by applying a logic 1 to pin 12 (s/h2 command). s/h2 employs a current-summing architecture that subtracts the output of s/h1 (the offset) from the output of the ccd (offset+video) while acquiring only the difference signal (i.e., the valid video). a logic 0 subsequently applied to pin 12 drives s/h2 into its hold mode, and after a brief transient settling time, the valid video signal appears at pin 22 (v out). timing notes see figure 2, typical timing diagram. it is advisable that neither of the CDS-1401's s/h amplifiers be in their sample/ figure 3. CDS-1401 in front of ads-ccd1201 at f clk = 1mhz s/h1 s/h2 start convert eoc output data data n-1 valid data n valid 30ns typ. 90ns typ. 73ns max. 35ns max. analog input for cds (pins 3 and 4 are tied) (ccd output) data n+1 valid 400ns 400ns offset (n+1) offset + video (n+1) offset (n+2) offset + video (n+2) 420ns reset reset
6 CDS-1401 ? ? for most sampling a/d's, the rising edge of the start-convert pulse drives the internal s/h into the hold mode under the assumption the s/h has already fully acquired and is tracking the input signal. in this case, the same edge can not be used to drive s/h2 into the hold mode and simultaneously initiate the a/d conversion. the output of s/h2 needs time to settle its sample-to-hold switching transient, and the input s/h of the a/d needs time to fully acquire its new input signal. as shown in figure 1, output line a/d clock1 (pin 18) is a slightly delayed version of the signal applied to pin 11 (s/h1 command), and a/d clock1 (pin 17) is its complement. a/d clock2 (pin 19) is a delayed version of the signal applied to pin 12 (s/h2 command), and a/d clock2 (pin 20) is its complement. any one of these signals, as appropriate, may be used to trigger the a/d conversion. figure 3 is a typical timing diagram for a CDS-1401 in front of datel's 12-bit, 1.2mhz sampling a/d, the ads-ccd1201. less than that of video signals, it may not be necessary for the allocated acquisition time of s/h1 to be as long as that of s/h2. as shown in the plot (figure 4) of acquisition times vs. input signal step size, the s/h's internal to the CDS-1401 acquire smaller-amplitude signals quicker than they acquire larger- amplitude signals. in "maximum-throughput" applications, assuming "asymmetric" timing can be accommodated, each s/h should only be given the time it requires, and no more, to acquire its input signal. leaving a s/h amp in the sample mode for a longer period of time has little added benefit. as an example, the graph shows that it takes 160ns to acquire a 500mv step to within 10mv of accuracy and 260ns to acquire a 500mv step to within 0.5mv of accuracy. the figures in this graph are typical values at room temperature. the CDS-1401 brings out 4 control lines that can be used to trigger an a/d converter connected to its output. if the a/d is a sampling type, system timing should be such that the a/d's input s/h amplifier is acquiring the output of the CDS-1401 at the same time the output is settling to its final value. figure 4. acquisition time versus accuracy and step size 160 180 200 220 240 260 280 300 320 340 012345678910 input step size (volts) acquisition time (ns) 0.5mv accuracy 1mv accuracy 2mv accuracy 5mv accuracy 10mv accuracy
7 ? ? CDS-1401 calibration procedure offset adjust (figure 5) offset and pedestal errors may be compensated for by applying external voltages to pin 1 (offset adjust v1) and/ or pin 9 (offset adjust v2) using either voltage-output dacs or potentiometers configured to appear as voltage sources. offset and pedestal errors may also be compensated for by applying external currents to pin 2 (offset adjust i1) and/ or pin 10 (offset adjust i2) by using either current-output dacs or potentiometers configured to appear as current sources. 1. connect pin 8 (s/h2 summing node) either directly to pin 7 (s/h1 rout) or through a 200 ohm potentiometer to pin 6 (s/h1 out). 2. tie pins 3 (analog input 1) and 4 (analog input 2) to pin 5 (analog ground). 3. adjust offset adjust v1 or offset adjust i1 (while s/h1 is in the hold mode) until pin 6 (s/h1 out) equals 0v. 4. adjust offset adjust v2 or offset adjust i2 (while s/h2 is in the hold mode) until pin 22 (vout) equals 0v. 5. to negate the effect of output droop on the offset-adjust process, each s/h must be continually switched between its sample and hold modes and adjusted so its output equals zero immediately after going into the hold mode. the sensitivity of the voltage offset adjustments is 100mv per volt . the sensitivity of the current offset adjustments is 1v per ma. pins 1, 2, 9 and 10 should be left open (floating) when not being used for offset adjustment. gross offset adjustment for gross offset adjustments use pin 2 (offset adjust i1) and/or pin 10 (offset adjust i2). all connections made to pin 2 and pin 10 should be very short because these are very sensitive points. sourcing 1ma into offset adjust i1 will cause a C1v offset change at pin 6 (s/h1 out). it will also cause a +1v offset change at pin 22 (v out) if pin 7 (s/h1 rout) is connected to pin 8 (s/h2 summing node). sourcing 1ma into offset adjust i2 will cause a C1v offset change at pin 22 (v out). gain matching adjustment (differential gain) between s/h1 and s/h2 the user can adjust the gain matching (differential gain) between s/h1 and s/h2 by leaving pin 7 (s/h1 rout) floating (open) and connecting a 200 ohm potentiometer between pin 6 (s/h1 out) and pin 8 (s/h2 summing node). note, offset adjustment should take place before gain matching adjustment. apply a full-scale input to both pins 3 (analog input 1) and 4 (analog input 2). adjust the 200 ohm potentiometer (with both s/h's in the sample mode) until pin 22 (v out) is 0v. if gain matching adjustment is not required, leave pin 6 (s/h1 out) floating (open) and tie pin 7 (s/h1 rout) to pin 8 (s/h2 summing node). figure 5. CDS-1401 typical connection diagram offset adjust v1 1 +15v C15v offset adjust i1 2 analog input 1 3 analog input 2 4 analog ground 5 s/h1 out 6 s/h1 rout 7 s/h2 summing node 8 offset adjust v2 9 +15v C15v offset adjust i2 10 s/h1 command 11 s/h2 command 12 200 w 0.1f 2.2f +15v + 0.1f 2.2f + C15v 0.1f 2.2f +5v + 24 23 22 21 20 19 18 17 16 15 14 13 analog ground v out analog ground a/d clock 2 a/d clock 2 a/d clock 1 a/d clock 1 +5v digital supply digital ground analog ground C15v analog supply +15v analog supply CDS-1401
CDS-1401 ? ? mechanical dimensions inches (mm) 24-pin ddip 24-pin surface mount 0.200 max. (5.080) 0.235 max. (5.969) 0.600 0.010 (15.240) 0.80 max. (20.32) 0.100 typ. (2.540) 0.100 (2.540) 0.018 0.002 (0.457) 0.100 (2.540) 0.040 (1.016) 1.31 max. (33.27) 112 13 24 1.100 (27.940) 0.190 max. (4.826) 0.010 (0.254) +0.002 C0.001 seating plane 0.025 ( 0.635 ) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.80 max. (20.32) 0.015 (0.381) max. radius for any pin 1.31 max. (33.02) 0.100 typ. (2.540) 0.100 (2.540) 0.210 max. (5.334) 0.040 (1.016) 0.020 typ. (0.508) 0.020 (0.508) 24 13 12 1 pin 1 index 0.130 typ. (3.302) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.060 typ. (1.524) 0.010 typ. (0.254) ? ? innov a tion and ex cellence datel, inc. 11 cabot boulevard, mansfield, ma 02048-1151 tel: (508) 339-3000 / fax: (508) 339-6356 for immediate assistance: (800) 233-2765 datel makes no representation that the use of its products in the circuits described herein, or the use of other technical info rmation contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. specifications are s ubject to change without notice. the datel logo is a registered datel, inc. trademark. ds-0315 10/96 datel (uk) ltd. tadley, england tel: (01256)-880444 datel s.a.r.l. montigny le bretonneux, france tel: 1-34-60-01-01 datel gmbh munchen, germany tel: 89-544334-0 datel kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-354-2025 iso 9001 i so 9001 registered operating analog package model temp. range input type csd-1401mc 0 to +70c 10v ddip CDS-1401mm C55 to +125c 10v ddip ordering information accessories hs-24 heat sink for CDS-1401 ddip models receptacles for pc board mounting can be ordered through amp inc., part number 3-331272-8 (component lead socket), 24 required. for mil-std-883 products, or availability of surface mount packaging, contact datel.
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